1. Field of the Invention
This invention relates to the mapping of data in relative address space into absolute address memory, and more particularly to the prediction of the absolute address segment in which the relative address data will be stored.
2. Description of the Prior Art
The memory required by modern data processing systems can be immense. In order to address all address locations within a memory, sufficient addressing bits must be provided to address the entire memory space. The number of address bits required is therefore directly proportional to the amount of memory desired. These address bits are typically part of a machine instruction, and comprise the address field of that instruction. In many data processing systems, more absolute address space exists in the system than can actually be addressed by a particular instruction, due to constraints on the number of bits in the instruction set. In order to avoid this problem, "relative addressing" can be used.
A relative address is the address formulated by determining the difference between a desired address and a known base or reference address. When the relative address is combined with the known base address, the absolute address may be accessed. The relative address may be part of the machine instruction where the absolute address could not, since the relative address requires fewer bits than the address of the resulting absolute address.
Where relative addressing is used, only a portion of the absolute address space may be accessed for a given base address. This is because the base address, which comprises a predetermined number of address bits, is a constant. For instance, for a thirty-two bit absolute address in which the base address comprises the least significant ten bits, only 2.sup.10 address locations (1024 address locations) can be accessed by the base address. If the relative address only contains six bits, then 2.sup.10 plus 2.sup.6 absolute address locations (1,088 address locations) can be accessed. However, the absolute address space contains 2.sup.32 address locations (4.3.times.10.sup.9 address locations). As can be seen, only 1,088 of 4.3.times.10.sup.9 address locations can be accessed using the given ten bit base address and a six bit base address. It may be desirable to only access contiguous address locations within a particular block of absolute memory space. Relative addressing will allow such a block to be accessed. Therefore, in order to access the remaining portion of the absolute memory space, additional base addresses are required.
The use of multiple base addresses will allow various blocks of absolute memory to be accessed. However, it must then be decided which of the base addresses is to be used in conjunction with the relative address to generate the absolute address. An absolute address could be calculated for each base address, but this requires separate adding circuitry for each base address used, and also requires multiplexing of these large generated addresses to choose the desired absolute addresses. This also increases the power consumption of the system. In order to avoid this problem, the present invention utilizes only one adding circuit, and selects one base address to be combined with the relative address to produce the absolute address.
The base address can be selected by comparing the relative address to predetermined base address boundaries. However, the present invention allows for the base address to be predicted, which decreases the time required to generate the absolute address. The prediction method used is based on the trend of recent base address selections, rather than overall statistical predictions. By following the trend of recent base address selections, memory activity such as data block transfers are predicted with greater accuracy than with overall statistical predictions. This results in an increase in system operating speed.
Therefore, the present invention allows for a reduction in real estate required, since only one adder is used. Accordingly, power consumption is reduced. Furthermore, the improved base prediction method increases system speed.